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| ML12210 Serial Input PLL Frequency Synthesizer Legacy Device: Motorola MC12210 The ML12210 is a 2.5 GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse-swallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications. The technology used allows for low power operation at a minimum supply voltage of 2.7 V. The device is designed for operation over 2.7 to 5.5 V supply range for input frequencies up to 2.5 GHz with a typical current drain of 9.5 mA. The low power consumption makes the ML12210 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 32/33 or 64/65 divide ratio. 16 1 SO 16 = -5P PLASTIC PACKAGE CASE 751B (SO-16) * Low Power Supply Current of 8.8 mA Typical for ICC and 0.7 mA Typical for Ip * Supply Voltage of 2.7 to 5.5 V * Dual Modulus Prescaler With Selectable Divide Ratios of 32/33 or 64/65 * On-Chip Reference Oscillator/Buffer * Programmable Reference Divider Consisting of a Binary 14-Bit Programmable Reference Counter * Programmable Divider Consisting of a Binary 7-Bit Swallow Counter and an 11-Bit Programmable Counter * Phase/Frequency Detector With Phase Conversion Function * Balanced Charge Pump Outputs * Dual Internal Charge Pumps for Bypassing the First Stage of the Loop Filter to Decrease Lock Time * Outputs for External Charge Pump * Operating Temperature Range of TA = -40 to 85C NOTE: Also available is the ML12202, a 1.1 GHz version of this function. CROSS REFERENCE/ORDERING INFORMATION MOTOROLA LANSDALE PACKAGE SO 16 MC12210D ML12210-5P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. MAXIMUM RATINGS (Note 1) Parameter Power Supply Voltage, Pin 4 Power Supply Voltage, Pin 3 Storage Temperature Range Symbol VCC Vp Tstg Value -0.5 to 6.0 VCC to 6.0 -65 to 150 Unit Vdc Vdc C NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Page 1 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. R 16 P 15 fOUT BISW 14 13 FC 12 LE 11 DATA 10 CLK 9 Pinout: 16-Lead Package (Top View) 1 2 3 4 VCC 5 Do 6 GND 7 LD 8 fIN OSCin OSCout VP PIN NAMES Pin OSCin OSCout VP VCC Do GND LD fIN CLK DATA LE I/O I O - - O - O I I I I Function Oscillator input. A crystal may be connected between OSCin and OSCout. It is highly recommended that an external source be ac coupled into this pin (see text). Oscillator output. Pin should be left open if external source is used Power supply for charge pumps (VP should be greater than or equal to VCC) VP provides power to the Do, BISW and P outputs Power supply voltage input. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge pump output. Do remains on at all times Ground Lock detect, phase comparator output Prescaler input. The VCO signal is AC-coupled into this pin Clock input. Rising edge of the clock shifts data into the shift registers Binary serial data input Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data stored in the shift register is transferred into the appropriate latch (depending on the level of control bit). Also, when LE is HIGH or OPEN, the output of the second internal charge pump is connected to the BISW pin Phase control select (with internal pull up resistor). When FC is LOW, the characteristics of the phase comparator and charge pump are reversed. FC also selects fp or fr on the fOUT pin Analog switch output. When LE is HIGH or OPEN ("analog switch is ON") the output of the second charge pump is connected to the BISW pin. When LE is LOW, BISW is high impedance Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable reference divider output; when FC is LOW, fOUT=fp, programmable divider output Output for external charge pump. Standard CMOS output level Output for external charge pump. Standard CMOS output level No connect 16-Lead Pkg Pin No. 1 2 3 4 5 6 7 8 9 10 11 20-Lead Pkg Pin No. FC I 12 BISW O 13 fOUT P R NC O O O - 14 15 16 - Page 2 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. Figure 1. ML12210 Block Diagram 15-BIT SHIFT REGISTER 15 15-BIT LATCH 14 1 PROGRAMMABLE REFERENCE DIVIDER OSCin OSCout CRYSTAL OSCILLATOR 14-BIT REFERENCE COUNTER fr PHASE/FREQUENCY DETECTOR CHARGE PUMP 1 LE LE DATA 7 CLK 7-BIT LATCH 7 CONTROL BIT DATA 18-BIT SHIFT REGISTER 11 DIVIDER OUTPUT MUX fOUT LD P R Do FC CHARGE PUMP 2 BISW 11-BIT LATCH 11 fIN PRESCALER 32/33 or 64/65 PROGRAMMABLE DIVIDER 7-BIT SWALLOW A-COUNTER 11-BIT PROGRAMMABLE N-COUNTER fp CONTROL LOGIC Page 3 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. DATA ENTRY FORMAT The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14-bit programmable reference divider plus the prescaler setting bit, and the 18-bit programmable divider. A rising edge of the clock shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable pin is HIGH or OPEN. Control bit: "H" = data is transferred into 15-bit latch of programmable reference divider "L" = data is transferred into 18-bit latch of programmable divider WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect the VCO. PROGRAMMABLE REFERENCE DIVIDER 16-bit serial data format for the programmable reference counter, "R-counter", and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15-bit shift register into the 15-bit latch which specifies the R divide ratio (8 to16383) and the prescaler divide ratio (SW=0 for /64/65, SW=1 for /32/33). An R divide ratio less than 8 is prohibited. For Control bit (C) = HIGH: SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT) MSB CONTROL BIT (LAST BIT) LSB S W R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 C SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE REFERENCE COUNTER (R-COUNTER) DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER Divide Ratio R 8 9 * 16383 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1 R 4 1 1 * 1 R 3 0 0 * 1 R 2 0 0 * 1 R 1 0 1 * 1 PRESCALER SELECT BIT Prescaler Divide Ratio P 64/65 32/33 SW 0 1 Page 4 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. PROGRAMMABLE DIVIDER 19-bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18-bit shift register into the 18-bit latch which specifies the swallow A-counter divide ratio (0 to 127) and the programmable N-counter divide ratio (16 to 2047). An N-counter divide ratio less than 16 is prohibited. For Control bit (C) = LOW: MSB (FIRST BIT) CONTROL BIT (LAST BIT) LSB N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 C SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE N-COUNTER SETTING BITS FOR DIVIDE RATIO OF SWALLOW A-COUNTER DIVIDE RATIO OF PROGRAMMABLE N-COUNTER Divide Ratio N 16 17 N 18 0 0 N 17 0 0 N 16 0 0 N 15 0 0 N 14 0 0 N 13 0 0 N 12 1 1 N 11 0 0 N 10 0 0 N 9 0 0 N 8 0 1 DIVIDE RATIO OF SWALLOW A-COUNTER Divide Ratio A 0 1 A 7 0 0 A 6 0 0 A 5 0 0 A 4 0 0 A 3 0 0 A 2 0 0 A 1 0 1 * 2047 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 127 * 1 * 1 * 1 * 1 * 1 * 1 * 1 DIVIDE RATIO SETTING fvco = [(P * N)+A] * fosc / R with A LE ts(CLE) ts(D) th(D) tCW tEW NOTES: Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK. ts(D) = Setup Time DATA to CLK ts(D) 10 ns th(D) = Hold Time DATA to CLK th(D) 20 ns tCW = CLK Pulse Width tCW 30 ns tEW = LE Pulse Width tEW 20 ns ts(CLE) = Setup Time CLK to LE ts(CLE) 30 ns Page 5 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. PHASE CHARACTERISTICS/VCO CHARACTERISTICS The phase comparator in the ML12210 is a high speed digital phase frequency detector circuit. The circuit determines the "lead" or "lag" phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input. Since these edges occur only once per cycle, the detector has a range of 2 radians. The phase comparator outputs are standard CMOS rail-to-rail levels (VP to GND for P and VCC to GND for R), designed for up to 20MHz operation into a 15pF load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics. The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are controlled by the FC pin. The polarity of the phase comparator outputs, R and P, as well as the charge pump output Do can be reversed by switching the FC pin. Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms H fr L H fp L H LD L Source Z Sink H L H P (FC = H) L Source Z Sink H L H P (FC = L) L NOTES: Do and BISW are current outputs. Phase difference detection range: -2 to +2 Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics. Isource + Isink = 4mA 4 4 Do (FC = H) BISW (LE = H or Open) R (FC = H) Do (FC = L) BISW (LE = H or Open) R (FC = L) Internal Charge Pump Gain Page 6 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. For FC = HIGH: fr lags fp in phase OR fp>fr in frequency When the phase of fr lags that of fp or the frequency of fp is greater than fr, the P output will remain in a HIGH state while the R output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180 out of phase condition. The signal on R indicates to the VCO to decrease in frequency to bring the loop into lock. fr leads fp in phase OR fp FC = HIGH or OPEN Do fp < fr fp > fr fp = fr (2) VCO INPUT VOLTAGE H L Z R L H L P L H H fOUT fr fr fr Do L H Z FC = LOW R H L L P H L H fOUT fp fp fp fOUT = fr fOUT = fp VCO OUTPUT FREQUENCY (1) NOTES: Z = High impedance When LE is HIGH or Open, BISW has the same characteristics as Do. Page 7 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. Legacy Applications Information Figure 6. Detailed Phase Comparator Block Diagram fr 0 R 1 fp 0 1 V LD PHASE COMPARATOR CHARGE PUMP 1 FC CHARGE PUMP 2 LE BISW PHASE FREQUENCY DETECTOR DOWN R UP P Do LOCK DETECT The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally HIGH. LD is designed to be the logical NORing of the phase frequency detector's outputs UP and DOWN. See Figure 6. In typical applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9. OSCILLATOR INPUT For best operation, an external reference oscillator is recommended. The signal should be AC-coupled to the OSCin pin through a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC-coupled signal must be between 500 and 2200 mV peak-to-peak. To optimize the phase noise of the PLL when used in this mode, the input signal amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the internal voltage reference. The device incorporates an on-chip reference oscillator/buffer so that an external parallel-resonant fundamental crystal can be connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum of 30 pF each including parasitic and stray capacitance). However, using the on-chip reference oscillator greatly increases the synthesized phase noise. DUAL INTERNAL CHARGE PUMPS ("ANALOG SWITCH") Due to the pure Bipolar nature of the ML12210 design, the "analog switch" function is implemented with dual internal charge pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time. When LE is HIGH or OPEN ("analog switch is ON"), the output of the second internal charge pump is connected to the BISW pin, and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is LOW, BISW is in a high impedance state and Do output is active. Figure 7. "Analog Switch" Block Diagram CHARGE PUMP 1 Do LPF-1 LPF-2 VCO CHARGE PUMP 2 LE BISW Page 8 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V; TA = -40 to +85C, unless otherwise noted.) Parameter Supply Current for VCC Symbol ICC Min - - Supply Current for VP IP - - Operating Frequency Operating Frequency (OSCin) fINmax fINmin FIN FOSC 2500 - - - Input Sensitivity fIN OSCin Input HIGH Voltage Input LOW Voltage CLK, DATA, LE, FC CLK, DATA, LE, FC VIN VOSC VIH VIL IIH IIL IOSC IIH IIL ISource6 ISink6 IHi-Z Output HIGH Voltage (LD, R, P, fOUT) Output LOW Voltage (LD, R, P, fOUT) Output HIGH Current (LD, R, P, fOUT) Output LOW Current (LD, R, P, fOUT) 1. VCC = 3.3 V, all outputs open. 2. VCC = 5.5 V, all outputs open. 3. VP = 3.3 V, all outputs open. VOH 200 500 0.7 VCC - - -10 - - - -75 -2.6 +1.4 -15 4.4 2.4 VOL - - IOH IOL -1.0 1.0 Typ 8.8 10.2 0.7 0.8 - - 12 - - - - - 1.0 -5.0 130 -310 1.0 -60 -2.0 +2.0 - - - - - - - Max 13.0 16.0 1.1 1.3 - 500 20 40 1000 2200 - 0.3 VCC 2.0 - - - 2.0 - -1.4 +2.6 +15 - - 0.4 0.4 - - nA V V V V mA mA MHz MHz MHz mVpp mVpp V V A A A A A mA VDo = Vp/2; Vp = 2.7 V VBISW = Vp/2; Vp = 2.7 V 0.5< VDO < Vp - 0.5 0.5 < VBISW < Vp - 0.5 VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V VCC = 5.5 V VCC = 5.5 V VCC = 5.5 V OSCin = VCC OSCin = VCC - 2.2 V mA Unit mA Note 1 Note 2 Note 3 Note 4 Note 5 Crystal Mode External Reference Mode Condition Input HIGH Current (DATA and CLK) Input LOW Current (DATA and CLK) Input Current (OSCin) Input HIGH Current (LE and FC) Input LOW Current (LE and FC) Charge Pump Output Current Do and BISW 4. Vp = 6.0 V, all outputs open. 5. AC coupling, FIN measured with a 1000 pF capacitor. 6. Source current flows out of the pin and sink current flows into the pin. Figure 8. Typical External Charge Pump Circuit Vp Figure 9. Typical Lock Detect Circuit VCC 10 k P 12 k 33 k EXTERNAL CHARGE PUMP OUTPUT R 12 k 10 k LD 0.01 F 10 k LOCK DETECT OUTPUT 100 k Page 9 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. Legacy Applications Information Figure 10. Typical Applications Example C1 1 OSCin R 16 EXTERNAL CHARGE PUMP (SEE FIGURE 8) LOW PASS FILTER (SEE FIGURE 11) VCO 2 C2 VP 3 VCC 100 pF 0.1 F 4 100 pF 0.1 F 5 OSCout P 15 CHARGE PUMP SELECTION (INTERNAL OR EXTERNAL) VP FOUT 14 VCC BISW 13 ML12210 Do FC 12 6 GND LE 11 LOCK DETECT LOCK DETECT CIRCUIT (SEE FIGURE 9) 7 LD DATA 10 47 k FROM CONTROLLER 8 1000 pF fin CLK 9 47 k C1, C2: Dependent on Crystal Oscillator Figure 11. Typical Loop Filter BISW Do OR EXTERNAL CHARGE PUMP R C VCO Page 10 of 11 www.lansdale.com Issue A ML12210 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS -A - 16 9 SO 16 = -5P PLASTIC PACKAGE (ML12210-5P) CASE 751B-05 (SO-16) ISSUE J -B - P 8 PL 0.25 (0.010) M 1 8 B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOW ABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 11 of 11 www.lansdale.com Issue A |
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